Nilquader and I decided to release our Verilog code (based on Nocash’s decryption of the algorithm) to “emulate” the ACID protection chip of the Amstrad Plus. So, you can now find it here (for more information have a look at the ACID article of the CPCWiki):
But this isn’t everything about the ACID. We also found a timing problem during the investigation with a logic analyzer, which you can see here:
You will find glitches on the /CCLR line which show that the SIN contact should be changed… All in all it is possible to use a fast flip-flop to change the SIN signal when such a glitch occurs (see picture below).
So, have fun with it :-).